SH7144 Datasheet, PDF (174/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
7
CW3
1
R/W Idle cycles at continuous access to CS3 space
This bit inserts an idle cycle and negates the CS3 signal to
make the bus cycle end obvious when accessing the CS3
space continuously.
0: No idle cycle inserted at continuous access to the CS3
space.
1: One idle cycle inserted at continuous access to the CS3
space.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
6
CW2
1
R/W Idle cycles at continuous access to CS2 space
This bit inserts an idle cycle and negates the CS2 signal to
make the bus cycle end obvious when accessing the CS2
space continuously.
0: No idle cycle inserted at continuous access to the CS2
space.
1: One idle cycle inserted at continuous access to the CS2
space.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
5
CW1
1
R/W Idle cycles at continuous access to CS1 space
This bit inserts an idle cycle and negates the CS1 signal to
make the bus cycle end obvious when accessing the CS1
space continuously.
0: No idle cycle inserted at continuous access to the CS1
space.
1: One idle cycle inserted at continuous access to the CS1
space.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
Rev. 2.0, 09/02, page 134 of 732