SH7144 Datasheet, PDF (660/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

3. Normal operation/software standby
AUDRST = 1
AUDMD
Input
AUDCK
(1) AUDMD = high: Input
(2) AUDMD = low: Output
AUDSYNC (1) AUDMD = high: Input
(2) AUDMD = low: Output
AUDRST
High-level input
AUDATA (1) AUDMD = high: Input/Output (2) AUDMD = low: Output
23.5.5 AUD Start-up Sequence
Follow the sequence described below to start up the AUD.
After selecting the AUD pin by the PFC, input at least three clocks to the AUDCK pin while
retaining the AUDRST pin at low level. Then, set the AUD reset bit (AUDSRST) in SYSCR to
clear the AUD reset. Low level input to the AUDRST pin and clock input to the AUDCK pin can
be started prior to the selection of the AUD pin by the PFC.
Rev. 2.0, 09/02, page 620 of 732