SH7144 Datasheet, PDF (508/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 15.2 Channel Select List
Bit 1
CH1
0
1
Bit 0
CH0
0
1
0
1
A/D0
AN0
AN1
AN2
AN3
Analog Input Channels
Single Mode
Scan Mode
A/D1
A/D0
A/D1
AN4
AN0
AN4
AN5
AN0, AN1
AN4, AN5
AN6
AN0 to AN2
AN4 to AN6
AN7
AN0 to AN3
AN4 to AN7
15.3.3 A/D Control Register_0 to 1 (ADCR_0 to ADCR_1)
ADCR for each module controls A/D conversion started by an external trigger signal and selects
the operating clock.
Bit Bit Name Initial Value R/W Description
7
TRGE
0
R/W Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG or an MTU trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
6
CKS1
0
R/W Clock Select 0 and 1
5
CKS0
0
R/W Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz.
Rev. 2.0, 09/02, page 468 of 732