SH7144 Datasheet, PDF (384/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Output Level Control/Status Register (OCSR): The output level control/status register (OCSR)
is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins
become high impedance.
Bit Bit Name Initial value R/W Description
15 OSF
0
R/(W)* Output Short Flag
This flag indicates that any one pair of the three
pairs of 2 phase outputs compared have
simultaneously become low level outputs.
Clear condition:
• By writing 0 to OSF after reading an OSF = 1
14 to 
All 0
10
9
OCE
0
Set condition:
• When any one pair of the three 2-phase outputs
simultaneously become low level
R
Reserved
These bits are always read as 0s and should always
be written with 0s.
R/W Output Level Compare Enable
This bit enables the start of output level
comparisons. When setting this bit to 1, pay
attention to the output pin combinations shown in
table 11.43, Mode Transition Combinations. When 0
is output, the OSF bit is set to 1 at the same time
when this bit is set, and output goes to high
impedance. Accordingly, bits 15 to 11 and bit 9 of
the port E data register (PEDR) are set to 1. For the
MTU output comparison, set the bit to 1 after setting
the MTU's output pins with the PFC. Set this bit only
when using pins as outputs.
When the OCE bit is set to 1, if OIE = 0 a high-
impedance request will not be issued even if OSF is
set to 1. Therefore, in order to have a high-
impedance request issued according to the result of
the output level comparison, the OIE bit must be set
to 1. When OCE = 1 and OIE = 1, an interrupt
request will be generated at the same time as the
high-impedance request: however, this interrupt can
be masked by means of an interrupt controller
(INTC) setting.
0: Output level compare disabled
1: Output level compare enabled; makes an output
high impedance request when OSF = 1.
Rev. 2.0, 09/02, page 344 of 732