SH7144 Datasheet, PDF (53/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 2 CPU
2.1 Features
• General-register architecture
 Sixteen 32-bit general registers
• Sixty-two basic instructions
• Eleven addressing modes
 Register direct [Rn]
 Register indirect [@Rn]
 Register indirect with post-increment [@Rn+]
 Register indirect with pre-decrement [@-Rn]
 Register indirect with displacement [@disp:4,Rn]
 Register indirect with index [@R0, Rn]
 GBR indirect with displacement [@disp:8,GBR]
 GBR indirect with index [@R0,GBR]
 Program-counter relative with displacement [@disp:8,PC]
 Program-counter relative [disp:8/disp:12/Rn]
 Immediate [#imm:8]
2.2 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four
32-bit system registers.
2.2.1 General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for
data processing and address calculation. R0 is also used as an index register. Several instructions
have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15.
CPUS201A_010020020700
Rev. 2.0, 09/02, page 13 of 732