SH7144 Datasheet, PDF (329/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Input Capture Signal Timing: Figure 11.59 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 11.59 Input Capture Input Signal Timing
Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.60 shows the
timing when counter clearing on compare match is specified, and figure 11.61 shows the timing
when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
TCNT
N
H'0000
TGR
N
Figure 11.60 Counter Clear Timing (Compare Match)
Rev. 2.0, 09/02, page 289 of 732