SH7144 Datasheet, PDF (178/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

9.6 Accessing External Space
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
9.6.1 Basic Timing
External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing of external
space access.
CK
Address
T1
T2
Read
Data
Write
Data
DACK
Figure 9.3 Basic Timing of External Space Access
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) accessed by RD signal are fetched by the LSI.
During a write, the WRHH (bits 31 to 24) , the WRHL (bits 23 to 16) , the WRH (bits 15 to 8),
and the WRL (bits 7 to 0) signal indicate the byte location to be written.
Rev. 2.0, 09/02, page 138 of 732