SH7144 Datasheet, PDF (486/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Master-reception mode Slave-transmission mode
SCL
(Master output)
8
9
SCL
(Slave output)
SDA
(Slave output)
A
SDA
[2]
(Master output) _R/W
1
2
3
4
5
6
7
8
9
1
2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data1
Bit7 Bit6
Data2
A
TDRE
IRIC
Interrupt-request Interrupt-request
generation
generation
[3]
Interrupt-request
generation
ICDRT
Data1
Data2
ICDRS
Data1
Data2
User processing [3] IRIC clear [3] ICDR write [3] ICDR write
[5] IRIC clear [5] ICDR write
Note: The numbers in brackets [ ] represent step numbers in the above procedural description.
Figure 14.11 An Example of the Timing of Operations in Slave-Transmission Mode
(MLS = 0)
Rev. 2.0, 09/02, page 446 of 732