SH7144 Datasheet, PDF (409/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Bit Bit Name Initial Value R/W Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and
data can be written to TDR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE =
1
• When the DMAC is activated by a TXI interrupt
request.
• When the DTC is activated by a TXI interrupt
request and transferred data to TDR while the
DISEL bit in DTMR of DTC is 0.
6
RDRF
0
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to RDRF after reading RDRF =
1
• When the DMAC is activated by a RXI interrupt
request.
• When the DTC is activated by an RXI interrupt
and transferred data from RDR while the DISEL
bit in DTMR of DTC is 0.
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
Rev. 2.0, 09/02, page 369 of 732