SH7144 Datasheet, PDF (14/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 8 Data Transfer Controller (DTC) ........................................................103
8.1 Features............................................................................................................................. 103
8.2 Register Descriptions ........................................................................................................ 105
8.2.1 DTC Mode Register (DTMR).............................................................................. 106
8.2.2 DTC Source Address Register (DTSAR) ............................................................ 108
8.2.3 DTC Destination Address Register (DTDAR)..................................................... 108
8.2.4 DTC Initial Address Register (DTIAR) ............................................................... 108
8.2.5 DTC Transfer Count Register A (DTCRA) ......................................................... 108
8.2.6 DTC Transfer Count Register B (DTCRB) ......................................................... 109
8.2.7 DTC Enable Registers (DTER)............................................................................ 109
8.2.8 DTC Control/Status Register (DTCSR)............................................................... 110
8.2.9 DTC Information Base Register (DTBR) ............................................................ 111
8.3 Operation .......................................................................................................................... 111
8.3.1 Activation Sources............................................................................................... 111
8.3.2 Location of Register Information and DTC Vector Table ................................... 112
8.3.3 DTC Operation .................................................................................................... 115
8.3.4 Interrupt Source ................................................................................................... 120
8.3.5 Operation Timing................................................................................................. 121
8.3.6 DTC Execution State Counts ............................................................................... 121
8.4 Procedures for Using DTC................................................................................................ 122
8.4.1 Activation by Interrupt......................................................................................... 122
8.4.2 Activation by Software ........................................................................................ 123
8.4.3 DTC Use Example ............................................................................................... 123
8.5 Cautions on Use ................................................................................................................ 124
8.5.1 Prohibition against DMAC/DTC Register Access by DTC................................. 124
8.5.2 Module Standby Mode Setting ............................................................................ 124
8.5.3 On-Chip RAM ..................................................................................................... 124
Section 9 Bus State Controller (BSC) ...............................................................125
9.1 Features............................................................................................................................. 125
9.2 Pin Configuration.............................................................................................................. 127
9.3 Register Descriptions ........................................................................................................ 127
9.4 Address Map ..................................................................................................................... 128
9.5 Description of Registers.................................................................................................... 130
9.5.1 Bus Control Register 1 (BCR1) ........................................................................... 130
9.5.2 Bus Control Register 2 (BCR2) ........................................................................... 132
9.5.3 Wait Control Register 1 (WCR1)......................................................................... 136
9.5.4 Wait Control Register 2 (WCR2)......................................................................... 137
9.5.5 RAM Emulation Register (RAMER)................................................................... 137
9.6 Accessing External Space ................................................................................................. 138
9.6.1 Basic Timing........................................................................................................ 138
9.6.2 Wait State Control ............................................................................................... 139
9.6.3 CS Assert Period Extension ................................................................................. 141
Rev. 2.0, 09/02, page xii of xxxviii