SH7144 Datasheet, PDF (242/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.3.2 Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Bit Bit Name Initial value R/W Description
7
—
1
—
Reserved
6
—
1
—
These bits are always read as 1 and should be
written with 1.
5
BFB
0
R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer
operation
4
BFA
0
R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer
operation
3
MD3
0
R/W Modes 0 to 3
2
MD2
0
R/W These bits are used to set the timer operating mode.
1
MD1
0
R/W See table 11.9 for details.
0
MD0
0
R/W
Rev. 2.0, 09/02, page 202 of 732