SH7144 Datasheet, PDF (218/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be
ascertained, and this facilitates handshake operations of transfer requests with the DMAC.
Cycle Steal Mode Operations: In cycle steal mode, DREQ sampling timing is the same
irrespective of dual or single address mode, or whether edge or low-level DREQ detection is used.
For example, DMAC transfer begins (figure 10.14), at the earliest, three cycles from the first
sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the
start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3)
transfer). At this point, if DREQ detection has not occurred, sampling is executed every cycle
thereafter.
As in figure 10.15, whatever cycle the CPU transfer cycle is, the next sampling begins from the
start of the transfer one bus cycle before the DMAC transfer begins.
Figure 10.14 shows an example of output during DACK read and figure 10.15 an example of
output during DACK write.
Figures 10.16 and 10.17 show cycle steal mode and single address mode. In this case, transfer
begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the
start of the transfer one bus cycle before the start of the first DMAC transfer. In single address
mode, the DACK signal is output during the DMAC transfer period.
Burst Mode, Dual Address, and Level Detection: Figures 10.18 and 10.19 show the DREQ
sampling timing in burst mode with dual address and level detection. DREQ sampling timing in
this mode is virtually the same as that of cycle steal mode.
For example, DMAC transfer begins (figure 10.18), at the earliest, three cycles after the timing of
the first sampling. The second sampling also begins from the start of the transfer one bus cycle
before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued,
DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC
transfer” may be a DMAC transfer.
In burst mode, the DACK output period is the same as that of cycle steal mode.
Burst Mode, Single Address, and Level Detection: DREQ sampling timing in burst mode with
single address and level detection is shown in figures 10.20 and 10.21.
In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle,
at the earliest, three cycles after timing of the first sampling. Data during this period is undefined,
and the DACK signal is not output. Nor is the number of DMAC transfers counted. The actual
DMAC transfer begins after one dummy bus cycle output.
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