SH7144 Datasheet, PDF (285/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 11.17 Example of Buffer Operation (2)
11.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
counters operates independently in phase counting mode.
Table 11.30 Cascaded Combinations
Combination
Channels 1 and 2
Upper 16 Bits
TCNT_1
Lower 16 Bits
TCNT_2
Rev. 2.0, 09/02, page 245 of 732