SH7144 Datasheet, PDF (199/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

10.3.5 DMAC Operation Register (DMAOR)
The DMAOR is a 16-bit readable/writable register that specifies the transfer mode of the DMAC
Bit
15 to
10
9
8
7 to 3
2
Bit Name Initial Value

All 0
PR1
0
PR0
0

All 0
AE
0
R/W
R
R/W
R/W
R
R/(W)*
Description
Reserved
These bits are always read as 0s and should
always be written with 0s.
Priority Mode 1 and 0
These bits determine the priority level of channels
for execution when transfer requests are made for
several channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: CH2 > CH0 > CH1 > CH3
11: Round robin mode
Reserved
These bits are read as 0s and should always be
written with 0s.
Address Error Flag
Indicates that an address error has occurred during
DMA transfer. If this bit is set during a data
transfer, transfers on all channels are suspended.
The CPU cannot write a 1 to the AE bit. Clearing is
effected by 0 write after 1 read.
0: No address error, DMA transfer enabled
Clearing condition:
Write AE = 0 after reading AE = 1
1: Address error, DMA transfer disabled
Setting condition:
Address error due to DMAC
Rev. 2.0, 09/02, page 159 of 732