SH7144 Datasheet, PDF (477/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 14.7 I²C Bus Data Format: Description of Symbols
S
SLA
R/W
A
DATA
P
This represents the start condition. The master device changes the level on SDA
from high to low while SCL is high.
This represents the slave address. The master device sends this to select the slave
device.
This represents the direction of transmission/reception. When the R/W bit is 1, data is
transferred from the slave to the master device. When the R/W bit is 0, data is
transferred from the master to the slave device.
This represents an acknowledgement. The receiving device sends this acknowledge
bit by setting the level on SDA to low (during master transmission, the slave returns
the acknowledge bits; during master reception, the master returns the acknowledge
bits).
This represents the transfer of data. The amount of bits to be transferred in each
such operation is set by the BC2 to BC0 bits of ICMR. The ICMR MLS bit determines
whether the data is transferred MSB first or LSB first.
This represents the stop condition. The master device changes the level on SDA from
low to high while SCL is high.
14.4.2 Operations in Master Transmission
In I²C bus format in the master transmission mode, the master device outputs the transmission
clock and data for transmission, and the slave device acknowledges its reception of data. The
following description gives the procedures for and operations of transmission.
1. Set the ICE bit in ICCR to 1. In addition, set the MLS and WAIT bits and the CKS2 to CKS0
bits of ICMR, and the IICX bit of SCRX, according to the operating mode.
2. Confirm that the bus is free by reading the BBSY flag in ICCR. Then set the MST and TRS
bits of ICCR to 1 to select the master-transmission mode. Then write 1 to BBSY and 0 to SCP.
This changes the level on SDA from high to low while SCL is high, and is thus the generation
of the start condition. The internal TDRE flag is thus set to 1, as are the IRIC and IRTR flags.
When the IEIC bit in ICCR has been set to 1, an interrupt request is generated for the CPU.
3. For a transfer in the I²C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the
first frame of data after the start condition includes the 7-bit slave address and the bit that
indicates the direction of the transfer operation as transmission or reception. The data for
transfer (slave address + R/W) is written to ICDR. In this case, the internal TDRE flag is
cleared to 0. The address data is transferred from ICDR to ICDRS, and the internal TDRE flag
is again set to 1. In this case, clear the IRIC flag to 0 so that the completion of this transfer can
be detected. The master device transmits the transmission clock signal and the data written in
the ICDR with the timing and in the order shown in figure 14.6. To acknowledge its selection,
the slave device that has been selected (that matches the slave address) sets the level on SDA
low in the 9th cycle of the transmission clock.
Rev. 2.0, 09/02, page 437 of 732