SH7144 Datasheet, PDF (754/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Table 2.4 T Bit
Page
20
2.5.1 Instruction Set by 38
Classification Branch
Instructions
Figure 2.4 Transitions 41
between Processing
States
3.1 Selection of
43
Operating Modes
Table 3.2 Clock Mode 44
Setting
4.3.1 Note on crystal 50
Resonator
Revisions (See Manual for Details)
Description amended.
ADD #1, R0 → ADD #-1, R0
Execution states amended.
Instruction Execution States T Bit
BF/S label 2/1*

Description amended.
=1
When an internal power-on
reset by WDT or internal
manual reset by
WDT occurs
Exception
processing state
Bus request
cleared
Bus request
generated
Exception
processing
Exception
processing
ends
= 1,
=1
NMI or IRQ interrupt
source occurs
Description added.
This LSI has four operating modes and four clock modes.
The operating mode is determined by the setting of MD3 to
MD0, and FWP pins. Do not change these pins during LSI
operation (while power is on). Do not set these pins in the
other way than the combination shown in table 3.1.
When power is applied to the system, be sure to conduct
power-on reset.
System clock output (CK) added.
Description amended.
A sufficient evaluation at the user’s site is necessary to use
the LSI, by referring the resonator connection examples
shown in this section, because various characteristics related
to the crystal resonator are closely linked to the user’s board
design. As the oscillator circuit’s circuit constant external
circuit’s component should be determined in consultation
with the resonator manufacturer. The design must ensure
that a voltage exceeding the maximum rating is not applied
to the oscillator pin.
Rev. 2.0, 09/02, page 714 of 732