SH7144 Datasheet, PDF (684/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register name
NO. of
abbreviation bits
Address
Module
Access size
NO. of Access
states
I²C bus control register
ICCR
8
H'FFFF8808
I²C
8, 16
Pφ reference
I²C bus status register
ICSR
8
H'FFFF8809
[Option]
8
B:2



H'FFFF880A to

W:4
H'FFFF880D
I²C bus data register
ICDR
8
H'FFFF880E*
8, 16
Second slave address register
SARX
8
H'FFFF880E*
8, 16
I²C bus mode register
ICMR
8
H'FFFF880F*
8
Slave address register
SAR
8
H'FFFF880F*
8



H'FFFF8810 to


H'FFFF8A4F
Instruction register
SDIR
16
H'FFFF8A50
H-UDI
8, 16, 32
Pφ reference
(Only in F-ZTAT
B:2
version)
W:2
Status register
SDSR
16
H'FFFF8A52
8, 16
L:4
Data register H
SDDRH
16
H'FFFF8A54
8, 16, 32
Data register L
SDDRL
16
H'FFFF8A56
8, 16


H'FFFF8A58 to

H'FFFFBFFF
Note: * Registers that can be read from/written to differ according to the setting of the ICE bit in
the IIC bus control register 0. In ICE=0, the registers read from/written to are the second
slave address register 0 and the slave address register 0. In ICE=1, they are the IIC bus
data register 0 and the IIC bus mode register 0.
Rev. 2.0, 09/02, page 644 of 732