SH7144 Datasheet, PDF (228/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 10.9 DMAC Internal Status
Item
Address Reload On
Address Reload Off
SAR
H'FFFF8428
H'FFFF842C
DAR
H'FFFFF004
H'FFFFF004
DMATCR
H'0000007C
H'0000007C
Bus mastership
Released
Maintained
DMAC operation
Halted
Processing continues
Interrupts
Not issued
Not issued
Transfer request source flag clear Executed
Not executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
they are executed regardless of whether the address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where
abnormal operation will result if it is executed in cycle steal mode.
4. Designate a multiple of four for the DMATCR value when using the address reload
function. There are cases where abnormal operation will result if anything else is
designated.
To execute transfers after the fifth one when the address reload is on, make the transfer request
source issue another transfer request signal.
10.5.4 Example of DMA Transfer between External Memory and SCI1 Transmit Side
(Indirect Address On)
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 transmit side is the transfer destination.
Table 10.10 indicates the transfer conditions and the setting values of each of the registers.
Rev. 2.0, 09/02, page 188 of 732