SH7144 Datasheet, PDF (49/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Type
Symbol
Bus control WRH
WRL
WAIT
Direct
memory
access
controller
(DMAC)
DREQ0
DREQ1
DRAK0
DRAK1
DACK0
DACK1
Multi function TCLKA
timer-pulse TCLKB
unit (MTU) TCLKC
TCLKD
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
I/O
Output
Output
Input
Input
Output
Output
Input
Name
Function
Write
upper half
Shows writing into the upper 8 bits (bits 15
to 8) of the external data.
Write lower
half
Shows writing into the lower 8 bits (bit7 to
bit0) of the external data.
Wait
Inserts the wait cycles into the bus cycle
when accessing the external spaces.
DMA transfer DMA request input pins from an external
request
device.
DREQ request Outputs an acknowledge signal to the
acknowledge external device that has input a DMA
transfer request signal.
DMA transfer Outputs a strobe to the I/O of the external
strobe
device that has input a DMA transfer
request signal.
External clock These pins input an external clock.
input for MTU
timer
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
MTU input
The TGRA_0 to TGRD_0 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 0)
MTU input
The TGRA_1 to TGRB_1 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 1)
MTU input
The TGRA_2 to TGRB_2 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 2)
MTU input
The TGRA_3 to TGRD_3 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 3)
MTU input
The TGRA_4 to TGRB_4 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 4)
Rev. 2.0, 09/02, page 9 of 732