SH7144 Datasheet, PDF (582/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register Bit
Initial
Bit Name Value R/W Description
PDCRL2 1
PDCRL1 1
PD1MD1 0
PD1MD0 0*³
R/W PD1 Mode
R/W Select the function of the PD1/D1 pin.
00: PD1 I/O (port)
01: D1 I/O (BSC)
10: Setting prohibited
11: Setting prohibited
PDCRL2 0
PDCRL1 0
PD0MD1 0
PD0MD0 0*³
R/W PD0 Mode
R/W Select the function of the PD0/D0 pin.
00: PD0 I/O (port)
01: D0 I/O (BSC)
10: Setting prohibited
11: Setting prohibited
Notes: 1. F-ZTAT only. Setting prohibited for the mask version.
2. The initial value is 1 in the on-chip ROM disabled 32-bit external-expansion mode.
3. The initial value is 1 in the on-chip ROM disabled external-expansion mode.
17.1.9 Port E I/O Register L (PEIORL)
The port E I/O register L (PEIORL) is a 16-bit readable/writable register that is used to set the
pins on port E as inputs or outputs. Bits PE15IOR to PE0IOR correspond to pins PE15 to PE0
(names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is
enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PD0),
TIOC pins are functioning as inputs/outputs of MTU, and SCK2 and SCK3 pins are functioning as
inputs/outputs of SCI. In other states, PEIORL is disabled.
A given pin on port E will be an output pin if the corresponding PEIORL bit is set to 1, and an
input pin if the bit is cleared to 0.
The initial value of PEIORL is H′0000.
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