SH7144 Datasheet, PDF (282/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

TCNT0 to TCNT2
values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
H'0000
Synchronous clearing by TGRB_0 compare match
Time
TIOC0A
TIOC1A
TIOC2A
Figure 11.12 Example of Synchronous Operation
11.4.3 Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 11.29 shows the register combinations used in buffer operation.
Table 11.29 Register Combinations in Buffer Operation
Channel
0
3
4
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
Rev. 2.0, 09/02, page 242 of 732