SH7144 Datasheet, PDF (385/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial value R/W Description
8
OIE
0
R/W Output Short Interrupt Enable
This bit makes interrupt requests when the OSF bit
of the OCSR is set.
00: Interrupt requests disabled
01: Interrupt request enabled
7 to 0 
All 0
R
Reserved
These bits are always read as 0s and should always
be written with 0s.
Note: * Only 0 can be written to write the flag.
11.9.4 Operation
Input Level Detection Operation
If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins
become high-impedance state. Note however, that these high-current pins become high-impedance
state only when general input/output function or MTU function is selected in these pins.
Falling Edge Detection: When a change from high to low level is input to the POE pins.
Low-Level Detection: Figure 11.115 shows the low-level detection operation. Sixteen continuous
low levels are sampled with the sampling clock established by the ICSR1. If even one high level is
detected during this interval, the low level is not accepted.
Sampling starts when detecting the falling edge of the POE pin. Thereby, negate the POE pin
when using POE function after sampling.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
Rev. 2.0, 09/02, page 345 of 732