SH7144 Datasheet, PDF (118/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

IRQnS
IRQnES
ISR.IRQnF
DTC
pins
Level
detection
Edge
detection
SQ
RESIRQn
R
(Acceptance of IRQn interrupt/DTC transfer end/
writing 0 after reading IRQnF = 1)
CPU interrupt
request
DTC starting request
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control
6.4.2 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
As a different interrupt vector is assigned to each interrupt source, the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A to J (IPRA to
IPRJ). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits
(I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
6.4.3 User Break Interrupt
A user break interrupt has a priority of level 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details about the user break interrupt, see
section 7, User Break Controller.
6.4.4 H-UDI Interrupt
Hitachi user debug interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-
UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are
held until accepted. H-UDI exception processing sets the interrupt mask level bits (I3-I0) in the
status register (SR) to level 15. For more details about the H-UDI interrupt, see section 22, Hitachi
User Debug Interface.
Rev. 2.0, 09/02, page 78 of 732