SH7144 Datasheet, PDF (172/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name Initial Value R/W Description
2
A2SZ
1
R/W CS2 space size
This bit specifies the CS2 space bus size in A2LG= 0.
0: Byte (8 bits)
1: Word (16 bits)
Note: In A2LG= 1, This bit is ignored and the CS2
bus size is longword (32bits).
1
A1SZ
1
R/W CS1 space size
This bit specifies the CS1 space bus size in A1LG= 0.
0: Byte (8 bits)
1: Word (16 bits)
Note: In A1LG= 1, This bit is ignored and the CS1
bus size is longword (32bits).
0
A0SZ
1
R/W CS0 space size
This bit specifies the CS0 space bus size in A0LG= 0.
0: Byte (8 bits)
1: Word (16 bits)
Note:
This bit is valid only in on-chip ROM enabled
mode. The CS0 space bus size is specified
with the mode pin in on-chip ROM disabled
mode. Even in on-chip ROM enabled mode,
this bit is ignored in A0LG= 1, and the CS0
space bus size is longword (32 bits).
9.5.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal
assert extension of each CS space.
Bit Bit Name Initial Value R/W Description
15 IW31
1
14 IW30
1
R/W Idle cycles in CS3 space cycles
R/W _{These bits insert idle cycles when the write cycle to the}
CS3 space comes after read access to the CS3 space, or
when continuous access is made to different CS spaces
after read access to the CS3 space.
00: No idle cycle inserted after access to the CS3 space
01: One idle cycle inserted after access to the CS3 space
10: Two idle cycles inserted after access to the CS3 space
11: Three idle cycles inserted after access to the CS3
space
Rev. 2.0, 09/02, page 132 of 732