SH7144 Datasheet, PDF (403/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.2 Input/Output Pins
Table 13.1 shows the pins for each SCI channel.
Table 13.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
SCI0 clock input/output
RxD0
Input
SCI0 receive data input
TxD0
Output
SCI0 transmit data output
1
SCK1
I/O
SCI1 clock input/output
RxD1
Input
SCI1 receive data input
TxD1
Output
SCI1 transmit data output
2
SCK2
I/O
SCI2 clock input/output
RxD2
Input
SCI2 receive data input
TxD2
Output
SCI2 transmit data output
3
SCK3
I/O
SCI3 clock input/output
RxD3
Input
SCI3 receive data input
TxD3
Output
SCI3 transmit data output
Notes: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel
1 designation.
13.3 Register Descriptions
The SCI has the following registers for each channel. For details on register addresses and register
states during each processing, refer to section 25, List of Registers.
Channel 0
• Serial mode register_0 (SMR_0)
• Bit rate register_0 (BRR_0)
• Serial control register_0 (SCR_0)
• Transmit data register_0 (TDR_0)
• Serial status register_0 (SSR_0)
• Receive data register_0 (RDR_0)
• Serial direction control register_0 (SDCR_0)
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