SH7144 Datasheet, PDF (589/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register Bit
Initial
Bit Name Value R/W Description
PECRL2 9
PE4MD1 0
R/W PE4 Mode
PECRL2 8
PE4MD0 0
R/W Select the function of the
PE4/TIOC1A/RXD3/AUDATA2 pin.
00: PE4 I/O (port)
01: TIOC1A I/O (MTU)
10: RXD3 input (SCI)
11: AUDATA2 I/O (AUD)*
PECRL2 7
PE3MD1 0
R/W PE3 Mode
PECRL2 6
PE3MD0 0
R/W Select the function of the
PE3/TIOC0D/DRAK1/AUDATA3 pin.
00: PE3 I/O (port)
01: TIOC0D I/O (MTU)
10: DRAK1 output (DMAC)
11: AUDATA3 I/O (AUD)*
PECRL2 5
PE2MD1 0
R/W PE2 Mode
PECRL2 4
PE2MD0 0
R/W Select the function of the
PE2/TIOC0C/DREQ1/AUDRST pin.
00: PE2 I/O (port)
01: TIOC0C I/O (MTU)
10: DREQ1 input (DMAC)
11: AUDRST input (AUD)*
PECRL2 3
PE1MD1 0
R/W PE1 Mode
PECRL2 2
PE1MD0 0
R/W Select the function of the
PE1/TIOC0B/DRAK0/AUDMD pin.
00: PE1 I/O (port)
01: TIOC0B I/O (MTU)
10: DRAK0 output (DMAC)
11: AUDMD input (AUD)*
PECRL2 1
PE0MD1 0
R/W PE0 Mode
PECRL2 0
PE0MD0 0
R/W Select the function of the
PE0/TIOC0A/DREQ0/AUDCK pin.
00: PE0 I/O (port)
01: TIOC0A I/O (MTU)
10: DREQ0 input (DMAC)
11: AUDCK I/O (AUD)*
Note: * F-ZTAT only. Setting prohibited for the mask version.
Rev. 2.0, 09/02, page 549 of 732