SH7144 Datasheet, PDF (390/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

ITI (interrupt
request signal)
*1
Internal reset
signal*2
Interrupt
control
Overflow
Clock
Reset
control
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Notes: 1. If this pin needs to be pulled-down,the resistance value must be 1M or higher.
2. The internal reset signal can be generated by register setting.
Power-on reset or manual reset can be selected.
Figure 12.1 Block Diagram of WDT
12.2 Input/Output Pin
Table 12.1 shows the pin configuration.
Table 12.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
Output
Function
Outputs the counter overflow signal in
watchdog timer mode
12.3 Register Descriptions
The WDT has the following three registers. For details, refer to section 25, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, refer to section 12.6.1, Notes on Register Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
Rev. 2.0, 09/02, page 350 of 732