SH7144 Datasheet, PDF (189/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 10 Direct Memory Access Controller (DMAC)
This LSI includes an on-chip four-channel direct memory access controller (DMAC). The DMAC
can be used in place of the CPU to perform high-speed data transfers among external devices
equipped with DACK (transfer request acknowledge signal), external memories, memory-mapped
external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and UBC).
Using the DMAC reduces the burden on the CPU and increases operating efficiency of the LSI as
a whole.
10.1 Features
• Four channels
• Four Gbytes of address space in the architecture
• Byte, word, or longword selectable data transfer unit
• 16,777,216 transfers, maximum
• Address mode
 Dual address mode or single address mode can be selected.
 Direct access or indirect access can be selected in dual address mode.
• Channel function: Transfer modes that can be set are different for each channel.
 Channel 0: Single or dual address mode. External requests are accepted.
 Channel 1: Single or dual address mode. External requests are accepted.
 Channel 2: Dual address mode only. Source address reload function is available.
 Channel 3: Dual address mode only. Direct address transfer mode and indirect address
transfer mode selectable.
• Transfer requests: There are three DMAC transfer activation requests, as indicated below.
 External request: From two DREQ pins. DREQ can be detected either by falling edge or by
low level.
 Requests from on-chip peripheral modules: Transfer requests from on-chip modules such
as SCI (request made to SCI_0 and SCI_1) or A/D (request made to A/D 1).
 Auto-request: The transfer request is generated automatically within the DMAC.
• Selectable bus modes: Cycle-steal mode or burst mode
• Two types of DMAC channel priority ranking: Fixed priority mode or round robin mode
• CPU can be interrupted when the specified number of data transfers are complete.
• Module standby mode can be set.
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