SH7144 Datasheet, PDF (507/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

15.3.2 A/D Control/Status Register_0 to 1 (ADCSR_0 to ADCSR_1)
ADCSR for each module controls A/D conversion operations.
Bit Bit Name Initial Value R/W Description
7
ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC or the DTC is activated by an
ADI interrupt and ADDR is read
6
ADIE
0
R/W A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
5

0
R
Reserved
This bit is always read as 0, and should only be
written with 0.
4
ADM
0
R/W Select the A/D conversion mode.
0: Single mode
1: Scan mode
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
3

1
R
Reserved
This bit is always read as 1, and should only be
written with 1.
2

0
R
Reserved
This bit is always read as 0, and should only be
written with 0.
1
CH1
0
R/W Channel select 1, 0
0
CH0
0
R/W Select analog input channels. See table 15.2.
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 09/02, page 467 of 732