SH7144 Datasheet, PDF (194/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W
Description
18 RL
0
(R/W)*² Request Check Level
Selects whether to output DRAK notifying external
device of DREQ received, with active high or active
low. This bit is valid only for CHCR_0 and CHCR_1.
For CHCR_2 and CHCR_3, this bit is always read
as 0 and should always be written with 0.
0: Output DRAK with active high
1: Output DRAK with active low
17 AM
0
(R/W)*² Acknowledge Mode
In dual address mode, selects whether to output
DACK in the data write cycle or data read cycle. In
single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid
only for CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and should
always be written with 0.
0: Outputs DACK during read cycle
1: Outputs DACK during write cycle
16 AL
0
(R/W)*² Acknowledge Level
Specifies whether to set DACK (acknowledge)
signal output to active high or active low. This bit is
valid only with CHCR_0 and CHCR_1. For
CHCR_2 and CHCR_3, this bit is always read as 0
and should always be written with 0.
0: Active high output
1: Active low output
15 DM1
0
14 DM0
0
R/W
Destination Address Mode 1, 0
R/W
These bits specify increment/decrement of the DMA
transfer destination address. These bit
specifications are ignored when transferring data
from an external device to address space in single
address mode.
00: Destination address fixed
01: Destination address incremented (+1 during 8-
bit transfer, +2 during 16-bit transfer, +4 during
32-bit transfer)
10: Destination address decremented (–1 during 8-
bit transfer, –2 during 16-bit transfer, –4 during
32-bit transfer)
11: Setting prohibited
Rev. 2.0, 09/02, page 154 of 732