SH7144 Datasheet, PDF (449/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
13.8.6 Constraints on DMAC and DTC Use
1. When using an external clock source for the serial clock, update TDR with the DMAC or the
DTC, and then after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If
a transmit clock is input in the first four Pφ clocks after TDR is written, an error may occur
(figure 13.21).
2. Before reading the receive data register (RDR) with the DMAC or the DTC, select the receive-
data-full (RXI) interrupt of the SCI as a start-up source.
SCK
t
TDRE
D0 D1 D2 D3 D4 D5 D6 D7
Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less.
Figure 13.21 Example of Clocked Synchronous Transmission with DMAC/DTC
13.8.7 Cautions on Clocked Synchronous External Clock Mode
1. Set TE = RE = 1 only when external clock SCK is 1.
2. Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed
from 0 to 1.
3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5 to 3.5 Pφ clocks from the rising
edge of the RxD D7 bit SCK input, but copying to RDR is not possible.
13.8.8 Caution on Clocked Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 Pφ clocks from the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
Rev. 2.0, 09/02, page 409 of 732