SH7144 Datasheet, PDF (166/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Figure 9.1 shows the BSC block diagram.
On-chip memory
control unit
Wait control
unit
Bus interface
RAMER
WCR1
WCR2
BCR1
to
Area control
unit
BCR2
Memory control
,
unit
,
BSC
WCR1: Wait control register 1
WCR2: Wait control register 2
BCR1: Bus control register 1
BCR2: Bus control register 2
RAMER: RAM emulation register
Note: Refer to section 19, Flash Memory (F-ZTAT Version), for RAMER.
Figure 9.1 BSC Block Diagram
Rev. 2.0, 09/02, page 126 of 732