SH7144 Datasheet, PDF (184/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
Address
T1
T2
Tidle
T1
T2
Data
CSn space access Idle cycle CSn space access
Figure 9.8 Example of Idle Cycle Insertion at Same Space Consecutive Access
9.8 Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device. It also has four internal bus masters, the CPU,
DMAC, DTC, and AUD. The priority for arbitrate the bus mastership between these bus masters
is:
Bus request from external device > AUD > DTC > DMAC > CPU
AUD does not acquire the bus mastership during DTC or DMAC burst transfer; it acquires the bus
mastership after DTC or DMAC burst transfer. AUD has the priority for the bus mastership to
DTC and DMAC if the CPU has the bus mastership. DMAC, continues operating even if DTC
requests the bus mastership during the read or the write period in DMAC dual address mode,
during burst transfer, or during operation in indirect address transfer mode.
A bus request by an external device should be input to the BREQ pin. When the BREQ pin is
asserted, this LSI releases the bus immediately after executing the current bus cycle. The signal
indicating that the bus has been released is output from the BACK pin.
However, the bus arbitration is not performed at the timing between the read cycle and the write
cycle of TAS instruction. In addition, bus arbitration is not performed during bus cycle if the
access size is greater than the data-bus size, for example, when a long-word access is made for an
8-bit size memory.
When an interrupt is generated and the CPU must process this interrupt, the LSI must take back
the bus mastership. For this purpose, this LSI has the IRQOUT pin used for the bus mastership
request signal. Before the LSI takes back the bus mastership, the IRQOUT signal is asserted.
When the IRQOUT signal is asserted, the device that asserted the external bus release request
negates the BREQ signal to release the bus mastership. This allows the bus mastership to return to
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