SH7144 Datasheet, PDF (337/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is
that after write, and on channels 3 and 4, before write.
Figures 11.74 and 11.75 show the timing in this case.
Pφ
Address
Write signal
Compare
match signal
Compare match
buffer signal
Buffer register
TGR write cycle
T1 T2
Buffer register
address
Buffer register write data
N
M
TGR
M
Figure 11.74 Contention between Buffer Register Write and Compare Match (Channel 0)
Rev. 2.0, 09/02, page 297 of 732