SH7144 Datasheet, PDF (155/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Activating
Source
Generator
Activating
Source
DTC Vector
Transfer
Address
DTE Bit Source
Transfer
Destination Priority
IIC
ICI
H'00000460 DTEG7 ICDR
Arbitrary* High
(receive) (receive)
Arbitrary* ICDR
(transmit) (transmit)
Reserved
—
H'00000462 to —
—
—
H'0000049F
Software
Write to
DTCSR
H'0400+
—
DTVEC[7:0]
Arbitrary* Arbitrary* Low
Note: * External memory, memory-mapped external devices, on-chip memory, on-chip peripheral
modules (excluding DMAC and DTC)
8.3.3 DTC Operation
Register information is stored in an on-chip RAM. When activated, the DTC reads register
information in an on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the RAM.
Pre-storage of register information in the RAM makes it possible to transfer data over any required
number of channels. The transfer mode can be specified as normal, repeat, and block transfer
mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single
activation source (chain transfer).
The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates
the transfer destination address. After each transfer, DTSAR and DTDAR are independently
incremented, decremented, or left fixed depending on its register information.
Rev. 2.0, 09/02, page 115 of 732