SH7144 Datasheet, PDF (20/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

15.4.6 External Trigger Input Timing............................................................................. 474
15.5 Interrupt Sources and DTC, DMAC Transfer Requests.................................................... 475
15.6 Definitions of A/D Conversion Accuracy......................................................................... 475
15.7 Usage Notes ...................................................................................................................... 477
15.7.1 Module Standby Mode Setting ............................................................................ 477
15.7.2 Permissible Signal Source Impedance ................................................................. 477
15.7.3 Influences on Absolute Accuracy ........................................................................ 477
15.7.4 Range of Analog Power Supply and Other Pin Settings...................................... 478
15.7.5 Notes on Board Design ........................................................................................ 478
15.7.6 Notes on Noise Countermeasures ........................................................................ 478
Section 16 Compare Match Timer (CMT) ........................................................481
16.1 Features............................................................................................................................. 481
16.2 Register Descriptions ........................................................................................................ 482
16.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 482
16.2.2 Compare Match Timer Control/Status Register 0 and 1(CMCSR0, 1)................ 483
16.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, 1).................................... 484
16.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, 1) .................... 484
16.3 Operation .......................................................................................................................... 484
16.3.1 Compare Match Counter Operation..................................................................... 484
16.3.2 CMCNT Count Timing........................................................................................ 485
16.4 Interrupts........................................................................................................................... 485
16.4.1 Interrupt Sources and DTC Activation ................................................................ 485
16.4.2 Compare Match Flag Set Timing......................................................................... 485
16.4.3 Compare Match Flag Clear Timing ..................................................................... 486
16.5 Usage Notes ...................................................................................................................... 487
16.5.1 Contention between CMCNT Write and Compare Match................................... 487
16.5.2 Contention between CMCNT Word Write and Counter Incrementation............. 487
16.5.3 Contention between CMCNT Byte Write and Counter Incrementation .............. 488
Section 17 Pin Function Controller (PFC) ........................................................489
17.1 Register Descriptions ........................................................................................................ 515
17.1.1 Port A I/O Register L, H (PAIORL, H) ............................................................... 516
17.1.2 Port A Control Registers L2, L1, and H (PACRL2, PACRL1, and PACRH) ..... 517
17.1.3 Port B I/O Register (PBIOR) ............................................................................... 525
17.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)...................................... 526
17.1.5 Port C I/O Register (PCIOR) ............................................................................... 529
17.1.6 Port C Control Register (PCCR) .......................................................................... 529
17.1.7 Port D I/O Registers L, H (PDIORL, H).............................................................. 531
17.1.8 Port D Control Registers L1, L2, H1, and H2
(PDCRL1, PDCRL2, PDCRH1, and PDCRH2) .................................................. 532
17.1.9 Port E I/O Register L (PEIORL).......................................................................... 542
17.1.10 Port E Control Registers L1 and L2 (PECRL1 and PECRL2)............................. 543
Rev. 2.0, 09/02, page xviii of xxxviii