SH7144 Datasheet, PDF (763/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
24.3.2 Software
Standby Mode
Page
630
24.4.5 DMAC, DTC, or 632
AUD Operation in
Sleep Mode
Table 26.2 DC
666,
Characteristics
667
Revisions (See Manual for Details)
Description amended.
• Clearing by the IRQ interrupt input
When the falling edge or rising edge of the IRQ pin
(selected by the IRQ7S to IRQ0S bits in ICR1 of the
interrupt controller (INTC) and the IRQ7ES[1:0] to
IRQ0ES[1:0] bits in ICR2) is detected, clock oscillation is
started*. This clock pulse is supplied only to the
watchdog timer (WDT). The IRQ interrupt priority level
should be higher than the interrupt mask level set in the
status register (SR) of the CPU before the transition to
software standby mode.
Added.
Item, Min, Typ, and Max values, and Measurement
conditions amended.
Item
Symbol
Input high-level RES, MRES,
V
IH
voltage (except NMI, FWP, MD3
Schmitt trigger to MD0, DBGMD
input voltage)
EXTAL
A/D port
Other input pins
Schmitt trigger IRQ7 to IRQ0,
V
T+
input voltage POE3 to POE0,
TCLKA to ⋅⋅⋅⋅⋅
V
T-
Output high- All output pins
V
OH
level voltage
Output low-
All output pins
V
OL
level voltage
Input
RES
C
in
capacitance
NMI
Min
V -0.5
CC
V -0.5
CC
2.2
2.2
V -0.5
CC

V -0.5
CC



Current
Normal Clock Icc

consumption*² operation 1:1
Clock

1:1/2
Sleep
Clock

1:1
Clock

1:1/2
Standby


Flash
Clock

program- 1:1
ming
Clock

1:1/2
Typ Max

V +0.3
CC
Unit
V
Measurement
Conditions

V +0.3 V
CC

AV + 0.3 V
CC

V +0.3 V
CC


V

0.5
V


V

0.4
V
I
OH
=
-200µA
IOL = 1.6mA

20

20
150 210
pF
Vin = 0 V
f = 1 MHz
pF
Ta = 25°C
mA
f = 40 MHz
160 220
mA
f = 50 MHz
110 170
mA
f = 40 MHz
120 180
mA
f = 50 MHz
3
50

500
150 210
160 220
µA
T
a
≤
50°C
µA
50°C
<
T
a
mA
V = 3.3V
CC
f = 40 MHz
mA
V = 3.3V
CC
f = 50MHz
Rev. 2.0, 09/02, page 723 of 732