|
SH7144 Datasheet, PDF (513/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine | |||
|
◁ |
A/D conversion time (tCONV)
A/D conversion start Analog input
delay time(tD) sampling time(tSPL)
ADCSR
write
cycle
PÏ
Address
Internal write
signal
ADST write timing
Analog input
sampling time
A/D converter
Idle state
Sample-and-hold A/D conversion
ADF
End of A/D conversion
Figure 15.2 A/D Conversion Timing
Table 15.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
CKS0 = 1
Item
Symbol Min Typ Max Min Typ Max
A/D conversion tD
start delay
31 â 62 15 â 30
Input sampling tSPL
time
â 256 â â 128 â
A/D conversion tCONV
time
1024 â 1055 515 â 530
Note: All values represent the number of states for PÏ.
CKS1 = 1
CKS0 = 0
CKS0 = 1
Min Typ Max Min Typ Max
7 â 14 3 â 6
â 64 â â 32 â
259 â 266 131 â 134
Rev. 2.0, 09/02, page 473 of 732
|
▷ |