SH7144 Datasheet, PDF (281/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Example of Synchronous Operation Setting Procedure: Figure 11.11 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
[2]
Synchronous clearing
Clearing
No
source generation
channel?
Yes
Select counter
[3]
clearing source
Start count
[5]
Set synchronous
[4]
counter clearing
Start count
[5]
<Synchronous presetting>
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to,
the same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 11.11 Example of Synchronous Operation Setting Procedure
Example of Synchronous Operation: Figure 11.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM
cycle.
For details of PWM modes, see section 11.4.5, PWM Modes.
Rev. 2.0, 09/02, page 241 of 732