SH7144 Datasheet, PDF (482/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.4.4 Operations in Slave Reception
In the slave-reception mode, the master device transmits the transmission clock and data, and the
slave device returns acknowledgements of reception. The following description gives the
procedures for and operations of receiving in slave mode.
1. Set the ICE bit of ICCR to 1. In addition, set the MLS bit of ICMR and the MST and TRS bits
of ICCR to the values required for the mode of operation.
2. When the output of a start condition by the master device is detected, the BBSY flag in ICCR
is set to 1.
3. When the slave address of the target device matches the address sent in the first frame after the
start condition, it has been designated to act as a slave device by the master device. When the
8th bit of data (R/W) is 0, the TRS bit in ICCR remains 0; the device receives in slave mode.
4. To acknowledge its selection, the slave device sets the level on SDA low on the 9th cycle of
the receive frame. The IRIC flag in ICCR is concurrently set to 1, which, when the IEIC bit in
ICCR is set to 1, generates an interrupt request for the CPU. When the internal RDRF flag has
been cleared to 0, the internal RDRF flag is set to 1, and receiving continues. While the
internal RDRF flag is set to 1, the slave device keeps the level on SCL to low from the falling
edge of the receive clock until the current datum has been read to ICDR.
5. ICDR is read and the IRIC flag in ICCR is cleared to 0. In this case, the RDRF flag is cleared
to 0.
Data is continuously received by repeatedly performing steps 4 and 5 above. When the stop
condition is detected, i.e., when the level on SDA goes from low to high while SCL is high, the
BBSY flag in ICCR is cleared to 0.
Rev. 2.0, 09/02, page 442 of 732