SH7144 Datasheet, PDF (485/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.4.5 Operations in Slave Transmission
In the slave-transmission mode, the slave device transmits data while the master device outputs the
reception clock and returns acknowledgements of reception. The following description gives the
procedures for and operations of transmitting in slave mode.
1. Set the ICE bit of ICCR to 1. In addition, set the MLS bit of ICMR and the MST and TRS bits
of ICCR to the values required for the mode of operation.
2. When the slave address of the target device matches the address sent in the first frame after the
start condition has been detected, the slave device sets the level on SDA low over the 9th cycle
of the clock to acknowledge its selection. The IRIC flag in ICCR is concurrently set to 1,
which, when the IEIC bit in ICCR is set to 1, generates an interrupt request for the CPU. When
the 8th bit of data (R/W) is 1, the TRS bit in ICCS is set to 1, and this automatically places the
device in the slave-transmission mode. In this case, the TDRE flag is set to 1. The slave device
sets the level on SCL low from the falling edge of the transmission clock until the first datum
for transmission is written to ICDR.
3. After 0 has been written to the IRIC flag, data is written to ICDR. In this case, the internal
TDRE flag is cleared to 0. The written data is transferred to ICDRS, and the internal TDRE
flag, the ICIR and IRTR flags are again set to 1. After clearing the IRIC flag to 0, the next
datum for transmission is written to ICDR. The slave device sequentially transmits the bits of
data written in ICDR, on the basis of the clock from the master device, and with the timing
shown in figure 14.11.
4. After the transmission of one frame has been completed, the IRIC flag in ICCR is set to 1 on
the rising edge of the 9th cycle of the transmission clock. When the internal TDRE flag is set
to 1, the slave device sets the level on SCL low from the falling edge of the transmission clock
until the next datum for transmission is written to ICDR. The master device sets SDA low on
the 9th cycle and then returns the acknowledgement that it has received the current datum. The
acknowledge signal is stored in the ACKB bit in ICSR and this makes it possible to confirm
that the transfer was completed normally. When the internal TDRE flag is 0, the bits in the
ICDR are transferred to ICDRS and transmission starts. The internal TDRE flag, and the IRIC
and the IRTR flags are then set to 1 again.
5. To continue with the transmission, clear the IRIC flag to 0 and write the next datum for
transmission to ICDR. In this case, the internal TDRE flag is cleared to 0.
Data is continuously transmitted by repeatedly performing steps 4 and 5 above. When completing
the transmission, write H’FF to ICDR. When the stop condition is detected, i.e., when the level on
SDA goes from low to high while SCL is high, the BBSY flag in ICCR is cleared to 0.
Rev. 2.0, 09/02, page 445 of 732