SH7144 Datasheet, PDF (524/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

16.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, 1)
The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for
generating interrupt requests.
The initial value of CMCNT is H′0000.
16.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, 1)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for
compare match with CMCNT.
The initial value of CMCOR is H′FFFF.
16.3 Operation
16.3.1 Compare Match Counter Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 16.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by CMCOR
compare match
H'0000
Time
Figure 16.2 Counter Operation
Rev. 2.0, 09/02, page 484 of 732