SH7144 Datasheet, PDF (623/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 19.4 Boot Mode Operation
Item
Boot mode
start
Host Operation
Processing Contents
Communications Contents
LSI Operation
Processing Contents
Branches to boot program at
reset-start.
Boot program initiation
Bit rate
adjustment
Continuously transmits data
H'00 at specified bit rate.
Transmits data H'55 when
data H'00 is received
error-free.
Receives data H'AA.
Transfer of
programming
control
program
Transmits number of bytes (N)
of programming control as
program to be transferred
2-byte data (lower byte
following upper byte)
Flash
memory
erase
Transmits 1-byte of
programming control program
(repeated for N times)
Boot program
erase error
Receives data H'AA.
H'00, H'00 ...... H'00
H'00
H'55
H'AA
Upper byte and
lower byte
Echoback
H'XX
Echoback
H'FF
H'AA
• Measures low-level period of receive
data H'00.
• Calculates bit rate and sets it in BRR
of SCI_1.
• Transmits data H'00 to host as
adjustment end indication.
Transmits data H'AA to host when
data H'55 is received.
Echobacks the 2-byte data received.
Echobacks received data to host and
also transfers it to RAM (repeated
for N times)
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA
to host. (If erase could not be done,
transmits data H'FF to host and
aborts operation.)
Branches to programming control
program transferred to on-chip RAM
and starts execution.
Table 19.5 Peripheral Clock (Pφ) Frequencies for which Automatic Adjustment of LSI Bit
Rate is Possible
Host Bit Rate
9,600 bps
19,200 bps
Peripheral Clock Frequency Range of LSI
4 to 40 MHz
8 to 40 MHz
Rev. 2.0, 09/02, page 583 of 732