SH7144 Datasheet, PDF (338/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

TGR write cycle
T1
T2
Pφ
Address
Buffer register
address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
Buffer register write data
N
M
TGR
N
Figure 11.75 Contention between Buffer Register Write and Compare Match
(Channels 3 and 4)
11.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 11.76 shows the timing in this case.
Pφ
Address
TGR read cycle
T1 T2
TGR address
Read signal
Input capture
signal
TGR
Internal data
bus
X
M
M
Figure 11.76 Contention between TGR Read and Input Capture
Rev. 2.0, 09/02, page 298 of 732