SH7144 Datasheet, PDF (643/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

22.3.2 Status Register (SDSR)
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. The
SDSR value can be output from TDO, but serial data cannot be written to SDSR via TDI. The
SDTRF bit is output by means of a one-bit shift. In a two-bit shift, the SDTRF bit is output first,
followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized in software standby mode.
Bit
15 to 12
Bit
Name

Initial R/W
value
All 0 R
11

1
R
10 to 1 
All 0 R
0
SDTRF 1
R/W
Description
These bits are always read as 0, and should only be
written with 0.
This bit is always read as 1, and should only be written
with 1.
This bit is always read as 0, and should only be written
with 0.
Serial Data Transfer Control Flag
Indicates whether H-UDI registers can be accessed by
the CPU. The SDTRF bit is initialized by the TRST
signal, but is not initialized in software standby mode.
0: Serial transfer to SDDR has ended, and SDDR can be
accessed
1: Serial transfer to SDDR is in progress
Rev. 2.0, 09/02, page 603 of 732