SH7144 Datasheet, PDF (637/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 21 RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU,
direct memory access controller (DMAC), data transfer controller (DTC), and advanced user
debugger (AUD)* by a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-
chip RAM. Data in the on-chip RAM can always be accessed in one cycle, providing high-speed
access that makes this RAM ideal for use as a program area, stack area, or data area. The on-chip
RAM is allocated to address H′FFFFE000 to H′FFFFFFFF. The contents of the on-chip RAM are
retained in both sleep and standby modes.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 24.2.2,
System Control Register (SYSCR).
Note: * Flash version only.
21.1 Usage Note
• Module Standby Mode Setting
RAM can be enabled/disabled by the module standby control register (MSTCR1). The initial
value enables RAM operation. RAM access is disabled by setting the module standby mode.
For details, see section 24, Power-Down Modes.
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