SH7144 Datasheet, PDF (397/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

12.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 12.5 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H’FF H’00
WOVF
Figure 12.5 Timing of Setting WOVF
12.5 Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 12.2 WDT Interrupt Source (in Interval Timer Mode)
Name
ITI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
DMAC/DTC Activation
Impossible
12.6 Usage Notes
12.6.1 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
TCNT and TCSR both have the same write address. The write data must be contained in the lower
byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure
12.6). This transfers the write data from the lower byte to TCNT or TCSR.
Rev. 2.0, 09/02, page 357 of 732