SH7144 Datasheet, PDF (760/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Page
Figure 13.13 Sample 397
Multiprocessor Serial
Reception Flowchart (2)
Revisions (See Manual for Details)
Figure amended.
Clear ORER and
FER flags in SSR to 0
13.6.2 SCI initialization 398
(Clocked Synchronous
mode)
14.5 Usage Notes
460
15.1 Features
463
Figure 15.1 Block
464
Diagram of A/D
Converter (For One
Module)
Figure 15.2 A/D
473
Conversion Timing
Table 15.3 A/D
473
Conversion Time
(Single Mode)
<End>
Title amended.
13.6.2 SCI initialization
→ 13.6.2 SCI initialization (Clocked Synchronous mode)
Usage notes added.
Description added.
• Conversion time: 5.4 µs per channel (at Pφ = 25 MHz
operation), 6.7µs per channel (at Pφ = 20 MHz operation)
Figure amended.
Legend:
ADCR_0 : A/D0 control register
ADCSR_0 : A/D0 control/status register
ADDR0
ADDR1
ADDR2
: A/D0 data register 0
: A/D0 data register 1
: A/D0 data register 2
ADDR3 : A/D0 data register 3
Figure amended.
ADCR_1 : A/D1 control register
ADCSR_1 : A/D1 control/status register
ADDR4 : A/D1 data register 4
ADDR5 : A/D1 data register 5
ADDR6 : A/D1 data register 6
ADDR7 : A/D1 data register 7
ADCSR
write
cycle
Pφ
Address
Internal write
signal
ADST write timing
A/D conversion start delay time amended.
Rev. 2.0, 09/02, page 720 of 732