SH7144 Datasheet, PDF (498/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

7. Points for caution when reading ICDR at the end of master reception
To halt the reception of data after a receive operation in the master-reception mode has been
completed, set the TRS bit to 1 and write 0 to BBSY and SCP. By doing so, the level on SDA
will be changed from low to high while SCL is high, that is, the stop condition will be
generated. The received data can be read by reading ICDR. If there is data in the buffer,
however, the data received in ICDRS cannot be transferred to ICDR. Therefore, the second-
byte of data cannot be read.
When reading of the second-byte of data is required, set the stop condition in the master-
reception mode (with the TRS bit being 0). When reading the received data, confirm that the
BBSY bit in ICCR is 0, the stop condition has been generated, and the bus is released. After
that, read the ICDR register while TRS is 0.
In this case, if an attempt is made to read the received data (data in ICDR) during the period
from the execution of the instruction (write 0 to BBSY and SCP of ICCR) that sets the stop
condition and the actual generation of the stop condition, it is not possible to generate the clock
correctly for a the subsequent master transmission.
Rewriting of the I²C control bit to change the mode of operation or setting of
transmission/reception, such as clearing of the MST bit after the completion of
transmission/reception by the master, must not take place in any period other than period (a)
(after confirming that the BBSY bit in ICCR has been cleared to 0) in figure 14.18.
SDA
SCL
Internal clock
BBSY bit
Bit 0
A
8
9
Stop condition
(a)
Master-reception mode
ICDR read-disabled
period
Start condition
Execution of the instruction _{Confirmation of stop-condition}
that sets the stop condition _{(reading 0 from BBSY)}
(writing 0 to BBSY and SCP)
Start condition set
Figure 14.18 Points for Caution in Reading Data Received by Master Reception
Rev. 2.0, 09/02, page 458 of 732