SH7144 Datasheet, PDF (265/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial value R/W Description
1 TGFB
0
R/(W)* Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for flag
clearing.
[Setting conditions]
• When TCNT = TGRB and TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGIB interrupt and the
DISEL bit of DTMR in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
0 TGFA
0
R/(W)* Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for flag
clearing.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGIA interrupt and the
DISEL bit of DTMR in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 09/02, page 225 of 732